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RT8209A/b/c 1 ds8209a/b/c-06 may 2011 www.richtek.com single synchronous buck controller general description the RT8209A/b/c pwm controller provides high efficiency, excellent transient response, and high dc output accuracy needed for stepping down high voltage batteries to generate low voltage cpu core, i/o, and chipset ram supplies in notebook computers. the constant-on-time pwm control scheme handles wide input/output voltage ratios with ease and provides 100ns ? instant-on ? response to load transients while maintaining a relatively constant switching frequency. the RT8209A/b/c achieves high efficiency at a reduced cost by eliminating the current-sense resistor found in traditional current mode pwms. efficiency is further enhanced by its ability to drive very large synchronous rectifier mosfets. the buck conversion allows this device to directly step down high voltage batteries for the highest possible efficiency. the RT8209A/b/c is intended for cpu core, chipset, dram, or other low voltage supplies as low as 0.75v. the RT8209A is in a wqfn-16l 3x3 package, the rt8209b is in a wqfn-14l 3.5x3.5 package and the rt8209c is available in a tssop-14 package. features z z z z z ultra-high efficiency z z z z z resistor programmable current limit by low side r ds(on) sense (lossless limit) z z z z z quick load step response within 100ns z z z z z 1% v fb accuracy over line and load z z z z z 4.5v to 26v battery input range z z z z z resistor programmable frequency z z z z z integrated bootstrap switch z z z z z integrated negative current limiter z z z z z over/under voltage protection z z z z z 4 steps current limit during soft-start z z z z z power good indicator z z z z z rohs compliant and halogen free applications z notebook computers z system power supplies z i/o supplies marking information ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. rt8209 package type qw : wqfn-16l 3x3 (w-type) qw : wqfn-14l 3.5x3.5 (w-type) c : tssop-14 lead plating system g : green (halogen free and pb free) z : eco (ecological element with halogen free and pb free) a : wqfn-16l 3x3 b : wqfn-14l 3.5x3.5 c : tssop-14 fh= : product code ymdnn : date code RT8209Agqw fh : product code ymdnn : date code RT8209Azqw a0= : product code ymdnn : date code rt8209bgqw rt8209cgc : product code ymdnn : date code rt8209cgc fh=ym dnn fh ym dnn a0=ym dnn rt8209c gcymdnn free datasheet http:///
RT8209A/b/c 2 ds8209a/b/c-06 may 2011 www.richtek.com functional pin description pin no. RT8209A r t8209b/c pin name pin function 1 3 vou t output voltage pin. connect to the output of pwm converter. vout is an input of the pwm controller. 2 4 vdd analog supply voltage input for the internal analog integrated circuit. bypass to gnd with a 1 f ceramic capacitor. 3 5 fb feedback input pin. c onnect fb to a resistor voltage divider from vout to gnd to adjust vout from 0.75v to 3.3v 4 6 pgood power good signal open-drain output of pwm converter. this pin will be pulled high when the output voltage is within the target range. 5, 14 17 (exposed pad) rt 8209b : 15 (exposed pad) nc no internal connection. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. typical application circuit to be continued pin configurations RT8209A (wqfn-16l 3x3) (top view) rt8209b (wqfn-14l 3.5x3.5) pgood fb vout vdd ugate phase vddp cs nc pgnd gnd lgate ton en/dem boot nc 12 11 10 9 13 14 15 16 1 2 3 4 8 7 6 5 nc 17 13 12 11 10 14 1 2 3 4 5 8 7 fb vdd ton vout ugate phase vddp cs gnd pgnd en/dem boot nc 15 9 6 pgood lgate boot ugate cs phase vddp lgate pgnd vdd vout ton en/dem gnd pgood fb 4 2 3 5 7 6 11 13 12 10 8 9 14 rt8209c (tssop-14) v d d p c s u g a t e fb RT8209A/b/c l g a t e b o o t p h a s e v o u t v i n vdd pgood p g o o d g n d t o n v d d p r 2 r 1 c 2 r t o n q 1 q2 c 1 v out = 1.05v en/dem r 6 p g n d c c m / d e m 2 5 0 k 1 0 1 0 0 k 1 f 1 8 k 0 r 4 r 5 c 3 0 0 . 1 f 4 . 5 v t o 2 6 v b s c 1 1 9 n 0 3 s c 4 1 0 f r 7 * c 7 * r 8 r 9 l 1 1 h c 5 * c 6 * 2 2 0 f b s c 1 1 9 n 0 3 s 1 2 k 3 0 k * : o p t i o n a l free datasheet http:///
RT8209A/b/c 3 ds8209a/b/c-06 may 2011 www.richtek.com pin no. RT8209A rt8209b/c pin name pin function 6 7 gnd analog ground. 7 8 pgnd power ground. 8 9 lgate low side n-mosfet gate driver output for pwm. this pin swings between gnd and vddp. 9 10 vddp vddp is the gate driver supply for external mosfets. bypass to gnd with a 1 f ceramic capacitor. 10 11 cs over current trip point set input. connect resistor from this pin to signal ground to set threshold for both over current and negative over current limit. 11 12 phase the ugate high side gate driver return. also serves as anode of over current comparator. 12 13 ugate high side n-mosfet floating gate driver output for the pwm converter. this pin swings between phase and boot. 13 14 boot bootstrap capacitor connection for pwm converter. connect to an external ceramic capacitor to phase. 15 1 en/dem enable/diode emulation mode control input. connect to vdd for diode-emulation mode, connect to gnd for shutdown and floating the pin for ccm mode. 16 2 ton on time/frequency adjustment pin. connect to phase through a resistor. ton is an input for the pwm controller. function block diagram min. t off qtrig 1-shot + - + - gm + - v ref s1 q latch s1 q latch + - ov + - uv 125% v ref 70% v ref + - 90% v ref ss timer thermal shutdown diode emulation drv drv on-time compute 1-shot cs fb vout vdd ugate phase vddp pgood pgnd lgate ton boot trig en/dem r q s ss (internal) gnd - + gm 10a + - free datasheet http:///
RT8209A/b/c 4 ds8209a/b/c-06 may 2011 www.richtek.com recommended operating conditions (note 4) z input voltage, v in ---------------------------------------------------------------------------------------------------------- 4.5v to 26v z supply voltage, v dd , v ddp ---------------------------------------------------------------------------------------------- 4.5v to 5.5v z junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z vdd, vddp, vout, en/dem, fb, pgood, to n to gnd ------------------------------------------------------- ? 0.3v to 6v z boot to gnd -------------------------------------------------------------------------------------------------------------- ? 0.3v to 38v z boot to phase ---------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z phase to gnd dc -------------------------------------------------------------------------------------------------------------------------- --- ? 0.3v to 32v < 20ns ---------------------------------------------------------------------------------------------------------------------- - ? 8v to 38v z ugate to phase dc -------------------------------------------------------------------------------------------------------------------------- --- ? 0.3v to 6v < 20ns ---------------------------------------------------------------------------------------------------------------------- - ? 5v to 7.5v z cs to gnd ------------------------------------------------------------------------------------------------------------------ ? 0.3v to 6v z lgate to gnd ------------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z lgate to gnd dc -------------------------------------------------------------------------------------------------------------------------- --- ? 0.3v to 6v < 20ns ---------------------------------------------------------------------------------------------------------------------- - ? 2.5v to 7.5v z pgnd to gnd -------------------------------------------------------------------------------------------------------------- ? 0.3v to 0.3v z power dissipation, p d @ t a = 25 c wqfn ? 16l 3x3 ------------------------------------------------------------------------------------------------------------ 1.471w wqfn ? 14l 3.5x3.5 ------------------------------------------------------------------------------------------------------- 1.667w tssop-14 ------------------------------------------------------------------------------------------------------------------- 0.741w z package thermal resistance (note 2) wqfn ? 16l 3x3, ja ------------------------------------------------------------------------------------------------------ 68 c/w wqfn ? 16l 3x3, jc ------------------------------------------------------------------------------------------------------ 7.5 c/w wqfn ? 14l 3.5x3.5, ja ------------------------------------------------------------------------------------------------- 60 c/w wqfn ? 14l 3.5x3.5, jc ------------------------------------------------------------------------------------------------- 7.5 c/w tssop-14, ja ------------------------------------------------------------------------------------------------------------- 135 c/w z lead temperature (soldering, 10 se c.) ------------------------------------------------------------------------------- 260 c z junction temperature ----------------------------------------------------------------------------------------------------- 150 c z storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ---------------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------------ 200v free datasheet http:///
RT8209A/b/c 5 ds8209a/b/c-06 may 2011 www.richtek.com to be continued electrical characteristics parameter symbol test conditions min typ max unit pwm controller i vdd v fb = 0.8v, en/dem = 5v -- 500 800 quiescent supply current i vddp v fb = 0.8v, en/dem = 5v -- 1 10 a i shdn_vdd en/dem = 0v -- 1 10 shutdown current i shdn_vddp en/dem = 0v -- -- 1 a fb reference voltage v ref v dd = 4.5v to 5.5v 0.742 0.750 0.758 v fb input bias current v fb = 0.75v ? 1 0.1 1 a output voltage range v out 0.75 -- 3.3 v on time v phase = 12v, v out = 2.5v, r ton = 250k ? 336 420 504 ns minimum off-time 250 400 550 ns vout shutdown discharge resistance en/dem = gnd -- 20 -- current sensing current limiter source current cs to gnd 9 10 11 a current comparator offset ? 10 -- 10 mv zero crossing threshold phase to gnd, en/dem = 5v ? 10 -- 5 mv fault protection gnd ? phase, v cs = 50mv 40 50 60 current limit threshold gnd ? phase, v cs = 200mv 190 200 210 mv current limit setting range cs to gnd 50 -- 200 mv output uv threshold uvp detect 60 70 80 % ovp threshold v fb _o v p ovp detect 120 125 130 % ov fault delay fb forced above ov threshold -- 20 -- s rising edge, pwm disabled below this level 4.1 4.3 4.5 v vdd under voltage lockout threshold hysteresis -- 80 -- mv current limit step duration at soft-start each step -- 128 -- clks uvp blanking time from en signal going high -- 512 -- clks thermal shutdown t sh dn hysteresis = 10 c -- 155 -- c driver on-resistance ugate drive source r ugatesr v boot ? v phase = 5v -- 2 5 ugate drive sink r ugatesk v boot ? v phase = 5v -- 1 5 lgate drive source r lgatesr lgate, high state -- 1 5 lgate drive sink r lgatesk lgate, low state -- 0.5 2.5 ugate driver source/sink current v ugate ? v ph ase = 2.5v, v boot ? v phase = 5v -- 1 -- a lgate driver source current v lgate = 2.5v -- 1 -- a lgate driver sink current v lgate = 2.5v -- 3 -- a lgate rising (v phase = 1.5v) -- 30 -- dead time ugate rising -- 30 -- ns (v in = 15v, v dd = v ddp = 5v, t a = 25 c, unless otherwise specified) free datasheet http:///
RT8209A/b/c 6 ds8209a/b/c-06 may 2011 www.richtek.com parameter symbol test conditions min typ max unit internal boot charging switch on resistance vddp to boot, 10ma -- -- 80 logic i/o en/dem low -- -- 0.8 en/dem high 2.9 -- -- en/dem logic input voltage en/dem float -- 2 -- v en/dem = vdd -- 1 5 logic input current en/dem = 0 ? 5 1 -- a pgood v fb with respect to reference, pgood from low to high 87 90 93 v fb with respect to reference, pgood from high to low -- 125 -- pgood threshold hysteresis -- 3 -- % fault propagation delay falling edge, fb forced below pgood trip threshold -- 2.5 -- s output low voltage i si nk = 1ma -- -- 0.4 v leakage current high state, forced to 5v -- -- 1 a note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective four layers thermal conductivity test board of jedec 51-7 thermal measurement standard. the case point of jc is on the expose pad for the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. free datasheet http:///
RT8209A/b/c 7 ds8209a/b/c-06 may 2011 www.richtek.com typical operating characteristics 2.5v efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) dem mode ccm mode v in = 12v, v out = 2.5v, en = vdd & floating. 1.05v efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) dem mode ccm mode v in = 12v, v out = 1.05v, en = vdd & floating. 1.05v efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) dem mode ccm mode v in = 20v, v out = 1.05v, en = vdd & floating. 2.5v efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) dem mode ccm mode v in = 20v, v out = 2.5v, en = vdd & floating. 1.05v efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) dem mode ccm mode v in = 8v, v out = 1.05v, en = vdd & floating. 2.5v efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) dem mode ccm mode v in = 8v, v out = 2.5v, en = vdd & floating. free datasheet http:///
RT8209A/b/c 8 ds8209a/b/c-06 may 2011 www.richtek.com 2.5v switching frequency vs. load current 0 50 100 150 200 250 300 350 400 450 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 2.5v switching frequency vs. load current 0 50 100 150 200 250 300 350 400 450 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 1.05v switching frequency vs. load current 0 50 100 150 200 250 300 350 400 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 1.05v switching frequency vs. load current 0 50 100 150 200 250 300 350 400 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 switching frequency vs. input voltage 0 50 100 150 200 250 300 350 400 450 500 6 1014182226 input voltage (v) switching frequency (khz) 1 v out = 2.5v ccm mode i out = 2a, en = floating v out = 1.05v dem mode ccm mode v in = 12v, v out = 1.05v, en = vdd & floating. dem mode ccm mode v in = 20v, v out = 1.05v, en = vdd & floating. dem mode ccm mode v in = 12v v out = 2.5v dem mode ccm mode en = vdd & floating v in = 20v v out = 2.5v en = vdd & floating switching frequency vs. r ton resistance 0 100 200 300 400 500 600 700 800 900 100 200 300 400 500 600 700 r ton resistance (k ? ) switching frequency (khz) 1 v out = 2.5v ccm mode v in = 15v, en = floating v out = 1.05v k free datasheet http:///
RT8209A/b/c 9 ds8209a/b/c-06 may 2011 www.richtek.com power on from en (ccm mode) time (400 s/div) en (2v/div) v out (1v/div) ugate (20v/div) pgood1 (5v/div) no load, v in = 12v, v out = 2.5v , en = floating power on from en (dem mode) time (400 s/div) en (2v/div) v out (1v/div) ugate (20v/div) pgood1 (5v/div) no load, v in = 12v, v out = 2.5v , en = vdd power on in short circuit time (2ms/div) vout (200mv/div) ugate (20v/div) i l (10a/div) lgate (5v/div) v in = 12v, en = floating (ccm mode) ovp (dem mode) time (100 s/div) vout (1v/div) ugate (20v/div) lgate (5v/div) v in = 12v, v out = 2.5v en = vdd, no load uvp (dem mode) time (20 s/div) vout (500mv/div) ugate (20v/div) i l (10a/div) lgate (5v/div) v in = 12v, v out = 1.05v en = vdd, no load shutdown input current vs. input voltage 0 0.2 0.4 0.6 0.8 1 7 9 11 13 15 17 19 21 23 25 input voltage (v) shutdown input current ( a) 1 en = gnd, no load free datasheet http:///
RT8209A/b/c 10 ds8209a/b/c-06 may 2011 www.richtek.com 2.5v load transient response time (20 s/div) i l (10a/div) v out_ac- coupled (100mv/div) ugate (20v/div) lgate (5v/div) v in = 12v, v out = 2.5v, en = vdd (ccm mode) mode transition ccm to dem time (40 s/div) v out_ac- coupled (100mv/div) ugate (20v/div) lgate (5v/div) v in = 12v, no load en (5v/div) mode transition dem to ccm time (40 s/div) v out_ac- coupled (100mv/div) ugate (20v/div) lgate (5v/div) v in = 12v, no load en (5v/div) free datasheet http:///
RT8209A/b/c 11 ds8209a/b/c-06 may 2011 www.richtek.com t on = 9.6p x r ton x (v out + 0.1) / (v in ? 0.3) + 50ns although this equation provides a good approximation to start with, the accuracy depends on each design and selection of the high side mosfet. and then the switching frequency is: r ton is the external resistor connected from the phase to ton pin. application information the RT8209A/b/c pwm controller provides high efficiency, excellent transient response, and high dc output accuracy needed for stepping down high voltage batteries to generate low voltage cpu core, i/o, and chipset ram supplies in notebook computers. richtek mach response tm technology is specifically designed for providing 100ns ? instant-on ? response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. the topology circumvents the poor load transient timing problems of fixed-frequency current-mode pwms while avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant off-time pwm schemes. the drv tm mode pwm modulator is specifically designed to have better noise immunity for such a single output application. pwm operation the mach response tm drv tm mode controller relies on the output filter capacitor's effective series resistance (esr) to act as a current sense resistor, so the output ripple voltage provides the pwm ramp signal. refer to the function block diagram, the synchronous ugate driver will be turned on at the beginning of each cycle. after the internal one-shot timer expires, the ugate driver will be turned off. the pulse width of this one shot is determined by the converter's input voltage and the output voltage to keep the frequency fairly constant over the input voltage range. another one-shot sets a minimum off-time (400ns typ.). on-time control the on-time one-shot comparator has two inputs. one input monitors the output voltage, while the other input samples the input voltage and converts it to a current. this input voltage proportional current is used to charge an internal on-time capacitor. the on-time is the time required for the voltage on this capacitor to charge from zero volts to v out , thereby making the on-time of the high side switch directly proportional to output voltage and inversely proportional to input voltage. the implementation results in a nearly constant switching frequency without the need a clock generator. mode selection (en/dem) operation the en/dem pin enables the supply. when en/dem is tied to vdd, the controller is enabled and operates in diode-emulation mode. when the en/dem pin is floating, the RT8209A/b/c will operate in forced-ccm mode. diode-emulation mode (en/dem = high) in diode-emulation mode, the RT8209A/b/c automatically reduces switching frequency at light-load conditions to maintain high efficiency. this reduction of frequency is achieved smoothly and without increasing vout ripple or load regulation. as the output current decreases from heavy-load condition, the inductor current is also reduced, and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. by emulating the behavior of diodes, the low side mosfet allows only partial of negative current when the inductor freewheeling current reach negative. as the load current is further decreased, it takes longer and longer to discharge the output capacitor to the level than requires the next ? on ? cycle. the on-time is kept the same as that in the heavy-load condition. in reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous condition. the transition load point to the light-load operation can be calculated as follows (figure 1) : where t on is on-time. out in on v f = vt ( ) ? ? in out load on vv it 2l free datasheet http:///
RT8209A/b/c 12 ds8209a/b/c-06 may 2011 www.richtek.com figure 1. boundary condition of ccm/dem the switching waveforms may appear noisy and asynchronous when light loading causes diode-emulation operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in dem noise vs. light-load efficiency is made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. the disadvantages for using higher inductor values include larger physical size and degrade load transient response (especially at low input-voltage levels). forced-ccm mode (en/dem = floating) the low noise, forced-ccm mode (en/dem = floating) disables the zero-crossing comparator, which controls the low-side switch on-time. this causes the low side gate drive waveform to become the complement of the high side gate-drive waveform. this in turn causes the inductor current to reverse at light loads as the pwm loop to maintain a duty ratio vout/vin. the benefit of forced- ccm mode is to keep the switching frequency fairly constant, but it comes at a cost. the no-load battery current can be up to 10ma to 40ma, depending on the external mosfets. current limit setting (ocp) RT8209A/b/c has cycle-by-cycle current limiting control. the current limit circuit employs a unique ? valley ? current sensing algorithm. if phase voltage plus the current limit threshold is below zero, the pwm is not allowed to initiate a new cycle (figure 2). in order to provide both good accuracy and a cost effective solution, the RT8209A/b/c supports temperature compensated mosfet r ds(on) sensing. the cs pin should be connected to gnd through the trip voltage setting resistor, r cs . the cs terminal source 10 a i cs current, and the trip level is set to the cs trip voltage, v cs can be calculated as following equation. v cs (mv) = r cs (k ) x 10 ( a) inductor current is monitored by the voltage between the pgnd pin and the phase pin, so the phase pin should be connected to the drain terminal of the low side mosfet. i cs has positive temperature coefficient to compensate the temperature dependency of the r ds(on) . pgnd is used as the positive current sensing node so pgnd should be connected to the source terminal of the bottom mosfet. as the comparison is done during the off state, v cs sets the valley level of the inductor current. thus, the load current at over current threshold, i load_oc , can be calculated as follows. figure 2. valley current limit i l t 0 i l, peak i lim i load i l t 0 t on slope = (v in -v out ) / l i l, peak i load = i l, peak / 2 mosfet gate driver (ugate, lgate) the high side driver is designed to drive high current, low r ds(on) n-mosfet(s). when configured as a floating driver, 5v bias voltage is delivered from vddp supply. the average drive current is proportional to the gate charge at vgs = 5v times switching frequency. the instantaneous drive current is supplied by the flying capacitor between boot and phase pins. a dead time to prevent shoot through is internally generated between high side mosfet off to low side mosfet on, and low side mosfet off to high side mosfet on. the low side driver is designed to drive high current, low r ds(on) n-mosfet(s). () ? cs ripple load_oc ds(on) in out out cs ds(on) in vi i = + r2 vv v v 1 = + r2lf v free datasheet http:///
RT8209A/b/c 13 ds8209a/b/c-06 may 2011 www.richtek.com the internal pull-down transistor that drives lgate low is robust, with a 0.5 typical on resistance. a 5v bias voltage is delivered from vddp supply. the instantaneous drive current is supplied by the flying capacitor between vddp and pgnd. for high current applications, some combinations of high and low side mosfets might be encountered that will cause excessive gate-drain coupling, which can lead to efficiency-killing, emi-producing shoot-through currents. this is often remedied by adding a resistor in series with boot, which increases the turn-on time of the high side mosfet without degrading the turn-off time (figure 3). figure 3. reducing the ugate rise time power good output (pgood) the power good output is an open-drain output and requires a pull-up resistor. when the output voltage is 25% above or 10% below its set voltage, pgood gets pulled low. it is held low until the output voltage returns to within these tolerances once more. in soft-start, pgood is actively held low and is allowed to transition high until soft-start is over and the output reaches 93% of its set voltage. there is a 2.5 s delay built into pgood circuitry to prevent false transitions. por, uvlo and soft-start power on reset (por) occurs when vdd rises above to approximately 4.3v, the RT8209A/b/c will reset the fault latch and preparing the pwm for operation. below 4.1 v (min) , the vdd under voltage-lockout (uvlo) circuitry inhibits switching by keeping ugate and lgate low. a built-in soft-start is used to prevent surge current from power supply input after en/dem is enabled. the maximum allowed current limit is segmented in 4 steps: 25%, 50%, 75% and 100% during this period, each step is 128 ugate clks. the current limit steps can eliminate the v out folded-back in the soft-start duration. output over voltage protection (ovp) the output voltage can be continuously monitored for over voltage protection. when the output voltage exceeds 25% of the set voltage threshold, over voltage protection is triggered and the low side mosfet is latched on. this activates the low side mosfet to discharge the output capacitor. the RT8209A/b/c is latched once ovp is triggered and can only be released by vdd or en/dem power on reset. there is a 20 s delay built into the over voltage protection circuit to prevent false transitions. output under voltage protection (uvp) the output voltage can be continuously monitored for under voltage protection. when the output voltage is less than 70% of the set voltage threshold, under voltage protection is triggered and then both ugate and lgate gate drivers are forced low. there is a 2.5 s delay built into the under voltage protection circuit to prevent false transitions. during soft-start, the uvp blanking time is 512 ugate clks. output voltage setting (fb) the output voltage can be adjusted from 0.75v to 3.3v by setting the feedback resistor r1 and r2 (figure 4). choose r2 to be approximately 10k , and solve for r1 using the equation: ?? ?? ?? out ref r1 v = v 1+ r2 where v ref is 0.75v.(typ.) phase lgate r1 r2 v out v in ugate vout fb gnd figure 4. setting vout with a resistor divider output inductor selection the switching frequency (on-time) and operating point (% ripple or lir) determine the inductor value as follows : boot ugate phase 10 v in ( ) ? on in out ir load(max) tvv l = li free datasheet http:///
RT8209A/b/c 14 ds8209a/b/c-06 may 2011 www.richtek.com where l ir is the ratio of peak-of-peak ripple current to the maximum average inductor current. find a low pass inductor having the lowest possible dc resistance that fits in the allowed dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough and not to saturate at the peak inductor current (i peak ) : ?? ?? ?? ?? ?? ?? ir peak load(max) load(max) l i = i + i 2 output capacitor selection the output filter capacitor must have low enough equivalent series resistance (esr) to meet output ripple and load- transient requirements, yet have high enough esr to satisfy stability requirements. the output capacitance must also be high enough to absorb the inductor energy while transiting from full-load to no-load conditions without tripping the overvoltage fault latch. although mach response tm drv tm dual ramp valley mode provides many advantages such as ease-of-use, minimum external component configuration, and extremely short response time, due to not employing an error amplifier in the loop, a sufficient feedback signal needs to be provided by an external circuit to reduce the jitter level. the required signal level is approximately 15mv at the comparing point. this generates v ripple = (v out / 0.75) x 15mv at the output node. the output capacitor esr should meet this requirement. output capacitor stability stability is determined by the value of the esr zero relative to the switching frequency. the point of instability is given by the following equation : sw esr out f 1 f = 2 esr c 4 do not put high value ceramic capacitors directly across the outputs without taking precautions to ensure stability. large ceramic capacitors can have a high esr zero frequency and cause erratic and unstable operation. however, it is easy to add sufficient series resistance by placing the capacitors a couple of inches downstream from the inductor and connecting vout or fb divider close to the inductor. there are two related but distinct ways including double-pulsing and feedback loop instability to identify the unstable operation. double-pulsing occurs due to noise on the output or because the esr is too low that there is not enough voltage ramp in the output voltage signal. this ? fools ? the error comparator into triggering a new cycle immediately after a 400ns minimum off-time period has expired. double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it may indicate the possible presence of loop instability, which is caused by insufficient esr. loop instability can result in oscillation at the output after line or load perturbations that can trip the over voltage protection latch or cause the output voltage to fall below the tolerance limit. the easiest method for stability checking is to apply a very zero-to-max load transient and carefully observe the output-voltage-ripple envelope for overshoot and ringing. it helps to simultaneously monitor the inductor current with ac probe. do not allow more than one ringing cycle after the initial step-response under- or over-shoot. thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature 125 c, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of RT8209A/b/c, where t j(max) is the maximum junction temperature of the die (125 c) and t a is the maximum ambient temperature. the junction to ambient thermal resistance ja is layout dependent. for wqfn-16l 3x3 packages, the thermal resistance ja is 68 c/w on the standard jedec 51-7 four layers thermal test board. for wqfn-14l 3.5x3.5 packages, the thermal resistance ja is 60 c/w on the standard jedec 51-7 four layers thermal test board. for tssop-14 packages, the thermal resistance ja is 135 c/w on the standard jedec 51-7 four layers thermal test board. the maximum power free datasheet http:///
RT8209A/b/c 15 ds8209a/b/c-06 may 2011 www.richtek.com figure 5. derating curves for RT8209A/b/c packages layout considerations layout is very important in high frequency switching converter design. if the layout is designed improperly, the pcb could radiate excessive noise and contribute to the converter instability. the following points must be followed for a proper layout of RT8209A/b/c. ` connect an rc low-pass filter from vddp to vdd, 1 f and 10 are recommended. place the filter capacitor close to the ic. ` keep current limit setting network as close as possible to the ic. routing of the network should avoid coupling to high voltage switching node. ` connections from the drivers to the respective gate of the high side or the low side mosfet should be as short as possible to reduce stray inductance. ` all sensitive analog traces and components such as vout, fb, gnd, en/dem, pgood, cs, vdd, and ton should be placed away from high voltage switching nodes such as phase, lgate, ugate, or boot nodes to avoid coupling. use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components. ` current sense connections must always be made using kelvin connections to ensure an accurate signal, with the current limit resistor located at the device. ` power sections should connect directly to ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). power components should be placed to minimize loops and reduce losses. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 wqfn -14l 3.5x3.5 four layers pcb wqfn -16l 3x3 tssop-14 dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (68 c/w) = 1.471w for wqfn-16l 3x3 packages p d(max) = (125 c ? 25 c) / (60 c/w) = 1.667w for wqfn-14l 3.5x3.5 packages p d(max) = (125 c ? 25 c) / (135 c/w) = 0.741w for tssop-14 packages the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for RT8209A/b/c packages, the figure 5 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. free datasheet http:///
RT8209A/b/c 16 ds8209a/b/c-06 may 2011 www.richtek.com outline dimension a a1 a3 d e 1 d2 e2 l b e see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 1.300 1.750 0.051 0.069 e 2.950 3.050 0.116 0.120 e2 1.300 1.750 0.051 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 16l qfn 3x3 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2 free datasheet http:///
RT8209A/b/c 17 ds8209a/b/c-06 may 2011 www.richtek.com dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 3.400 3.600 0.134 0.142 d2 1.950 2.150 0.077 0.085 e 3.400 3.600 0.134 0.142 e2 1.950 2.150 0.077 0.085 e 0.500 0.020 e1 1.500 0.060 l 0.300 0.500 0.012 0.020 w-type 14l qfn 3.5x3.5 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options free datasheet http:///
RT8209A/b/c 18 ds8209a/b/c-06 may 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com 14-lead tssop plastic package l e1 e e a a2 a1 b d dimensions in millimeters dimensions in inches symbol min max min max a 1.000 1.200 0.039 0.047 a1 0.050 0.150 0.002 0.006 a2 0.800 1.050 0.031 0.041 b 0.190 0.300 0.007 0.012 d 4.900 5.100 0.193 0.201 e 0.650 0.026 e 6.300 6.500 0.248 0.256 e1 4.300 4.500 0.169 0.177 l 0.450 0.750 0.018 0.030 free datasheet http:///

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